This invention relates to a wafer exposure method adopting a step and repeat exposure method of a projection system, particularly a reduction projection system and an apparatus for carrying out the same.
With the progress of high integration LSI techniques, the importance of microlithography is increasing. The precision of microlithography greatly depends upon the performance of the exposure apparatus. Recently, the performance of the exposure apparatus has been strikingly improved, and step and repeat exposure apparatus of projection type, particularly reduction projection type, has been developed and is regarded to be an effective apparatus for lithography of line widths of the order of 1 .mu.m.
FIG. 1 shows the construction of a well-known step and repeat exposure apparatus. Referring to FIG. 1, to the top of a stage 1 which is movable in X- and Y-direction, is secured a wafer chuck 2 for securing a wafer to the stage 1. Above the stage 1, an optical column 3 including an optical system for reducing mask patterns is disposed. The optical column 3 is provided near the edge of its top with two marks 4a and 4b for being aligned with alignment marks of a mask to be described later. Right above the optical column 3, a light source 5 is disposed at a predetermined distance therefrom. Further, the optical column 3 is provided with an alignment system 6 on its side wall. The alignment system 6 includes a body 7 provided at the bottom with marks 8a and 8b for being aligned with the alignment marks of the mask to be described later and microscopes 9a and 9b provided on top of the body 7 for observing the state of alignment with the marks 8a and 8b with the alignment marks of the wafer. In the alignment system 6 of this kind, a mirror or a half mirror may be provided between the marks 8a and 8b and the microscopes 9a and 9b, and an alignment monitor 10 uses the mirror or half mirror to observe the state of alignment between the marks 8a and 8b and the alignment marks of the alignment mask of wafer. The side of the stage 1 and the side of the optical column 3 are provided with marks 11a and 11b for effecting alignment of the two in the Y-direction.
Now, the method of wafer exposure with the reduction projection type step and repeat exposure apparatus described above will be described. The mask 12 is aligned with the optical column 3 by aligning the alignment marks 13a and 13b provided on a mask 12 having a desired mask pattern with the marks 4a and 4b provided on the optical column 3 near the edge of its top. With the reduction projection exposure system described above, the mask pattern of the mask 12 is projected on a reduced scale on a wafer. Therefore, with the reduction of the mask pattern the out-of-alignment between the mask 12 and optical column 3 is also reduced, and thus alignment departure from the alignment between the mask 12 and optical system 3 gives rise to no problem.
After the wafer 14 is secured to the wafer chuck 2, alignment between the wafer 14 and alignment system 6 is effected. More particularly, alignment marks 15a and 15b provided on the wafer 14 are aligned with the marks 8a and 8b of the main body 7 by moving the wafer 14 while observing it with the microscopes 9a and 9b or the alignment monitor 10. The alignment system 6 is secured to the optical column 3 at a predetermined position thereof, and thus the wafer 14 is indirectly aligned with the optical column 3 and mask 12.
After the alignment between the wafer 14 and alignment system 6 has been completed, the stage 1 is moved in the Y-direction along a rail (not shown) to effect alignment between the stage 1 and optical system 3 such that the wafer 14 is positioned directly beneath the optical column 3 as shown by double dot and bar line in FIG. 1. The alignment between the stage 1 and optical column 3 in the Y-direction may be automatically effected with a laser interferometer by making use of the mark 11a of the stage 1 and the mark 11b of the optical column.
After the alignment between the mask 12 and wafer 14 has been obtained, the step and repeat process is effected by moving the wafer 14 in the X- and Y-directions. For every step, light is projected from the light source 5 to illuminate the mask 12, and a reduced-scale pattern 16 of the mask pattern of the mask 12 is repeatedly projected on the wafer 14 as shown in FIG. 2.
After the exposure is ended, the stage 1 is returned to the initial position (i.e., the position at which the alignment between the wafer 14 and alignment system 6 had been effected), and then the wafer is replaced with a new one. Usually, the mask has one or more chip mask patterns, and the number of patterns 16 projected onto the wafer 14 is thus the product of the number of the chips of the mask and the number of times of repeat.
With the step and repeat exposure system as described above, the area of the wafer 14 on which light is projected in one shot (i.e., pattern 16) is small, the resolution can be very much improved, compared to a one-to-one projection system.
However, the prior art step and repeat exposure method as described above has the following drawback. While the wafer is usually provided with two cross marks as alignment marks as mentioned earlier and shown in FIGS. 1 to 3, the distance l between the two is fixed to a predetermined value peculiar to the exposure apparatus. Such two alignment marks at a fixed distance from each other are given to the wafer by the following method.
At the time of the step and repeat exposure in a first photolithography step (which is usually a step of forming element regions and field regions), two marks 18a and 18b are transferred together with patterns of element regions and field regions to each of predetermined regions 16 of a wafer 14 as shown in FIG. 4B by using a mask 12 as shown in FIG. 4A, which is provided with alignment marks 13a and 13b for alignment with respect to the exposure system, i.e., optical column, and also marks 17a and 17b for transfer to wafer, the marks 17a and 17b being provided in a transfer region. In this case, the distance l between two marks 18a and 18b enclosed in circles as shown in FIG. 4B is ns+t=l where s is the interval of the step (i.e., width 16 of the transfer region) and t is the distance between two marks 18a and 18b in each region 16 (n being the largest integral number meeting l.gtoreq.ns). Thus, the marks 18 a and 18b can be used as alignment marks 15a and 15b of the wafer 14 shown in FIG. 3.
When the ratio l/s is an integral number, t=0. In this case, the marks 17a and 17b of the mask 12 overlap each other. In this case, only a single mark is needed to the transfer region of the mask 12, which is convenient in view of the manufacture of the mask pattern. However, this is a rare case, and usually two marks 17a and 17b have to be provided at a distance of t/.alpha. (.alpha. being the reduction factor of transfer) in the transfer region of the mask 12. This has been a serious problem in the manufacture of the mask pattern. In the LSI mask pattern, the dimensions of the chip are made as small as possible in order to increase the mass production property and also from the necessity of accommodation in a package of a given size. Therefore, in many cases the surface of the chip is filled with transistors and metallization. For this reason, considerable difficulties are encountered from the IC layout standpoint to find a space for providing a mark at a predetermined distance from the other mark even if the space for providing the other mark is found. Further, as shown in FIG. 4B, there are only two marks that can be used as the alignment marks on the wafer, whereas marks 18a and 18b are provided two for each of the transfer regions 16, most of which are thus unnecessary. This is undesired from the standpoint of reducing the dimensions of the LSI layout.
In order to solve the above problems, it has been the practice to effect photoetching for the formation of the alignment marks prior to the photoetching for the formation of the element regions and field regions. For example, as shown in FIGS. 5A and 5B, an oxide film 19 is grown atop the wafer 14, and an oxide film pattern is formed by transferring a mark pattern only in two regions 16a and 16b where the necessary mark is to be provided. With this oxide film pattern as a mask, the wafer 14 is etched to form engraved alignment marks 15a' and 15b'. By this method, it is no longer necessary to provide marks on chips where transistors or the like are formed. On the demerit side, however, it is necessary to carry out an additional photoetching step.
In the meantime, the characteristics of a semiconductor device often vary depending upon the position of the chip in the wafer or with individual wafers. For this reason, it is important to be able to discriminate the positions of chips in the wafer and also the individual wafers even after division into pellets particularly in a stage of development of a semiconductor device. For example, the length of a gate or the size of Al metallization may vary between a chip from a central portion of a wafer and a chip from an edge portion thereof due to non-uniformity of the thickness of a resist film coated on the wafer surface or the non-uniformity of etching. Further, the stress in the wafer and also accompanying defects vary between the central portion and edge portion of the wafer.
In the prior art method of manufacture of semiconductor devices, however, the same pattern is transferred to all the chips, so that the resultant pellets cannot be distinguished from one another at all. This means that when evaluating the characteristics of a device, it is impossible to know whether the relevant pellet is from the central portion or edge portion of the wafer, and this is an obstacle in the development of devices. A similar obstacle is encountered in case when it is desired to measure differences of the characteristics of individual devices by conducting experiments with different process conditions set for different wafers or different lots because it is impossible to tell which wafers the individual devices are made from.